1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, more particularly, the plating of wafers within Back-End-Of-Line (BEOL) processing.
2. Description of the Related Art
Integrated circuits formed on semiconductor wafers typically include a large number of circuit elements, which form an electric circuit. In addition to active devices such as, for example, field effect transistors and/or bipolar transistors, integrated circuits can include passive devices such as resistors, inductors and/or capacitors.
The semiconductor manufacturing process typically includes two major components, namely the Front-End-of-Line (FEOL), which includes the multilayer process of forming semiconductor devices (transistors, etc.) on a semiconductor substrate, and the Back-End-Of-Line (BEOL), which includes the metallization after the semiconductor devices have been formed. Like all electronic devices, semiconductor devices in a microchip, such as an integrated circuit (IC), need to be electronically connected through wiring. In an integrated circuit, such wiring is done through multilayer metallization on top of the multilayered semiconductor devices formed on the semiconductor substrate. The complexity of this wiring becomes appreciable as there may be hundreds of millions or more semiconductor devices (e.g., transistors in particular) formed on a single IC. Proper connection of these devices is accomplished by multilayer metallization. Each metallization layer consists of a grid of metal lines sandwiched between one or more dielectric layers for electrical integrity. In fact, manufacturing processes can involve multiple metallization layers.
The interconnects in an integrated circuit represent a dominant factor in determining system performance and power dissipation. Thus, improving the functionality and performance capability of various metallization systems has become important in designing modern semiconductor devices. One example of such improvements is the enhanced use of copper metallization systems in integrated circuit devices and the use of so-called “low-k” dielectric materials (materials having a dielectric constant less than 3) in such devices. Copper metallization systems/interconnects exhibit improved electrical conductivity as compared to, for example, prior art metallization systems using aluminum for the conductive lines and vias. Using a lower resistivity interconnect material decreases the interconnect RC delay which, in turn, increases the operation speed of the integrated circuit. The use of low-k dielectric materials also tends to improve the signal-to-noise ratio (S/N ratio) by reducing crosstalk as compared to other dielectric materials with higher dielectric constants.
Copper is a material that is difficult to etch using traditional masking and etching techniques. Thus, conductive copper structures, e.g., conductive lines or vias, in modern integrated circuit devices are typically formed using known single or dual damascene techniques. In general, the damascene technique involves (1) forming a trench/via in a layer of insulating material, (2) depositing one or more relatively thin barrier layers, (3) forming copper material across the substrate and in the trench/via, and (4) performing a chemical mechanical polishing process to remove the excess portions of the copper material and the barrier layer positioned outside of the trench/via to define the final conductive copper structure. The copper material is typically formed by performing an electrochemical copper deposition process (copper plating) after a thin conductive (for example, copper) seed layer is deposited by physical vapor deposition on a barrier layer.
However, in advanced semiconductor nodes, the conductive seed layer deposited prior to copper plating is formed as a very thin layer, providing a relatively high electrical resistivity. This leads to a high lateral resistance gradient over the wafer to be plated which, in turn, may result in relatively poor plating conditions, particularly in the center of the wafer. FIGS. 1a and 1b illustrate the problem of a voltage drop arising across a wafer surface due to the lateral resistance gradient caused by resistive current paths on the surface of a wafer in an electrochemical plating bath. As shown in the top view of FIG. 1a, a wafer 100 comprising multiple dies 110 separated from each other by die seals 120 exhibits a voltage drop in a plating both from the wafer surface to the wafer center due to highly resistive portions of current paths on the surface of the wafer to be plated.
As shown in FIG. 1b, the wafer may have a network of conducting structures 130 in form of electrical contacts connecting to semiconductor devices, for example, as transistors, memory cells, etc. The conducting structures 130 may be formed in a stack of metallization layers 140. The wafer shown in FIG. 1a comprises a top layer 150 comprising some dielectric material. Particularly, the top layer 150 has openings, vias or trenches 160 that, for example, may be formed in the context of dual-damascene processing. The opening, vias or trenches 160 are coated by some seed layer 170. In particular, between the die seals 120, a highly resistive current path results on the surface of the wafer 100. Current flow during a process of copper plating in a plating bath is indicated in FIG. 1b by the arrows and the letter “I”. However, particularly across the die seals 120, a highly resistive current path forms that inhibits a homogeneous current distribution during electroplating and, thus, a significant voltage drop across the semiconductor wafer resulting in inhomogeneous plating conditions.
The present disclosure provides an enhanced wafer structure with respect to the distribution of plating currents applied to the surface of a wafer, as well as a method of manufacturing such a semiconductor wafer.